This invention relates to solid state switching circuits and, more particularly, to such circuits which employ a power field effect transistor as the solid state switching element.
Advances in the technology of power field effect transistors (PFET) which have increased voltage capabilities to greater than 1Kv and current ratings in the hundreds of amperes, have made the use of PFETs advantageous in solid state relays and power controllers. With the low power drive requirements of PFETs, it is theoretically possible to control kilowatts of load power with microwatts or milliwatts of gate power. However, the minimum amount of gate drive power that can be realized is constrained by the PFET gate input characteristic that is highly resistive for DC or steady-state conditions but highly capacitive for AC or dynamic conditions. When a PFET is used in a power controller, a load is energized by applying a gate signal to the PFET and de-energized by removing the gate signal. The input resistance of the PFET gate circuit is on the order of megohms or more and has a negligible effect on the dynamic operation of the PFET. However, the input capacitance, which may be 1,000 pfds or greater, must be considered. Consequently, the gate voltage, V.sub.g, response to drive signal changes is determined by the following expression: EQU V.sub.g =V.sub.d (1-e.sup.-t/Req.Ceq)
where V.sub.d is the drive voltage, R.sub.eq is determined by the control circuit resistances, and C.sub.eq is determined by the control circuit and the PFET gate circuit capacitances. From this expression, it can be seen that the gate voltage change to drive signal step changes will be exponential voltage rises and decays at rates determined by the circuit resistance and capacitance values that consequently affect PFET time delay and switching rate responses.
In a basic PFET gate drive circuit, a drive voltage is applied to a gate resistor that is connected in series with the PFET gate terminal. The gate and drive circuit time constant will be the same for both turn-on and turn-off. If it is desired to speed up the turn-off time without changing the turn-on time, then the gate resistor can be bypassed with a reverse bias diode and discharge resistor to decrease the turn-off time.
In some applications, particularly high voltage DC and multiple pole power switch applications, it is desirable to provide isolated gate drive control signals. Cost and reliability considerations dictate that the drive circuit be as simple as possible.
For power controller applications, it is desirable to provide a soft turn-on and turn-off or di/dt load current control in order to minimize electromagnetic interference and ringing and to help limit fault currents. However, these controlled, slower switching times also increase the dissipation in the PFET which must be kept within its safe operating area capability to prevent a catastrophic failure.
It is therefore desirable to devise a power field effect transistor drive circuit that provides independent control of turn-on and turn-off switching speeds, while operating at low power for high efficiency and to enable the use of integrated circuit logic devices for providing the gate drive voltage.